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CDB5531/32/33/34 CDB5531/32/33/34 Evaluation Board and Software
Features
l RS-232
General Description
The CDB5531/32/33/34 is an inexpensive tool designed to evaluate the functionality and performance of the CS5531/32/33/34. The CS5531/32/33/34 Datasheet should be read and consulted when using the CDB5531/32/33/34 evaluation board. The evaluation board includes a 2.5V voltage reference, an 80C51 microcontroller, an RS232 transceiver, and firmware. The 8051 controls the serial communication between the evaluation board and the PC, enabling quick and easy access to all of the CS5531/32/33/34's registers and functions. The included PC software contains algorithms for Data Capture, Time Domain Analysis, Histogram Analysis, and Frequency Domain Analysis. ORDERING INFORMATION CDB5531/32/33/34 Evaluation Board
Serial Communication with PC l On-board 80C51 Microcontroller l On-board Voltage Reference l Lab Windows/CVI Evaluation Software
- Register Setup & Chip Control - FFT Analysis - Time Domain Analysis - Noise Histogram Analysis
l On-board
Data SRAM l Integrated RS-232 Test Modes l Supports the CS5531, CS5532, CS5533, and CS5534 ADCs.
VOLTAGE REFERENCE VA+ REF+ REFVAVA+ VAAGND DGND VD+ Vu+
SENSESENSE+ LEDs AINBAINB+ AINCAINC+ AIND+ AINDAINA+ AINAAGUARD CRYSTAL 4.9152 MHz CRYSTAL 22.1148 MHz CS SDI SDO SCLK CS5531 CS5532 CS5533 CS5534 TEST SWITCHES 80C51 Microcontroller
RESET CIRCUITRY
RS232 TRANSCEIVER
RS232 CONNECTOR
32k x 8 SRAM
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2001 (All Rights Reserved)
JUL `01 DS289DB2 1
CDB5531/32/33/34
TABLE OF CONTENTS
1. HARDWARE ............................................................................................................................. 4 1.1 Introduction ........................................................................................................................ 4 1.2 Evaluation Board Overview ................................................................................................ 4 1.2.1 Analog Section ...................................................................................................... 4 1.2.2 Digital Section ....................................................................................................... 5 1.2.3 CS5531/32/33/34 Serial Interface ......................................................................... 5 1.2.4 Power Supply Section ........................................................................................... 5 1.2.5 Headers, Jumpers, and Dip Switches ................................................................... 5 2. SOFTWARE ............................................................................................................................ 13 2.1 Installation Procedure ...................................................................................................... 13 2.2 Using the Software ........................................................................................................... 13 2.3 Selecting and Testing a COM Port .................................................................................. 13 2.4 Selecting a Part ............................................................................................................... 14 2.5 Register Access in the Setup Window ............................................................................. 14 2.6 Data Collection Window Overview ................................................................................... 15 2.7 Config Window ................................................................................................................. 16 2.8 Collecting Data Sets ........................................................................................................ 16 2.9 Saving and Printing Data ................................................................................................. 17 2.10 Retrieving Saved Data From a File ................................................................................ 17 2.11 Plot Options Window ...................................................................................................... 17 2.12 Analyzing Data ............................................................................................................... 17 2.13 Histogram Information .................................................................................................... 18 2.14 Frequency Domain Information ...................................................................................... 18 2.15 Time Domain Information ............................................................................................... 18 3. PCB LAYOUT ......................................................................................................................... 23
Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/
IBM is a registered trademark of International Business Machines Inc. LabWindows and CVI are registered trademarks of National Instruments Corporation. MICROWIRE is a trademark of National Semiconductor Corporation. Motorola is a registered trademark of Motorola Inc. SPI is a registered trademark of International Business Machines Inc. Windows 95 is a registered trademark of Microsoft Corporation. Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
2
CDB5531/32/33/34
LIST OF FIGURES
Figure 1. Analog Section Schematic - Part 1 .................................................................................. 8 Figure 2. Analog Section Schematic - Part 2 .................................................................................. 9 Figure 3. Digital Section Schematic - Part 1 ................................................................................. 10 Figure 4. Digital Section Schematic - Part 2 ................................................................................. 11 Figure 5. Power Supply Connection Schematic............................................................................ 12 Figure 6. Start-Up Window............................................................................................................ 19 Figure 7. Setup Window................................................................................................................ 20 Figure 8. Channel Setup Register Window ................................................................................... 20 Figure 9. Calibration Window ........................................................................................................ 21 Figure 10. Data Collection Window: Time Domain Analysis ......................................................... 21 Figure 11. Data Collection Window: FFT Analysis........................................................................ 22 Figure 12. Data Collection Window: Histogram Analysis .............................................................. 22 Figure 13. Top Silkscreen ............................................................................................................. 24 Figure 14. Top Side Layout........................................................................................................... 25 Figure 15. Bottom Side Layout...................................................................................................... 26
3
CDB5531/32/33/34
1. HARDWARE 1.1 Introduction
The CDB5531/32/33/34 evaluation board provides a quick means of evaluating the CS5531/32/33/34 Analog-to-Digital Converters (ADCs). The CS5531/32/33/34 are highly integrated Analogto-Digital Converters (ADCs) which use chargebalance techniques to achieve 16-bit (CS5531/33) and 24-bit (CS5532/34) performance. The ADCs come as either two-channel (CS5531/32) or fourchannel (CS5533/34) devices and include a very low noise chopper-stabilized instrumentation amplifier (6 nV/Hz @ 0.1 Hz) with selectable gains of 1x, 2x, 4x, 8x, 16x, 32x, and 64x. These ADCs also include a fourth order modulator followed by a digital filter which provides twenty selectable output word rates of 6.25 Hz, 7.5 Hz, 12.5 Hz, 15 Hz, 25 Hz, 30 Hz, 50 Hz, 60 Hz, 100 Hz, 120 Hz, 200 Hz, 240 Hz, 400Hz, 480 Hz, 800 Hz, 960 Hz, 1.6 kHz, 1.92 kHz, 3.2 kHz and 3.84 kHz (XIN = 4.9152 MHz). The CS5531/32/33/34 are highly integrated devices. The devices' datasheets should be read thoroughly and understood before using the CDB5531/32/33/34 evaluation board. CS5531/32/33/34 to an IBM compatible PC with an RS-232 interface. To accomplish this, the board comes equipped with an 80C51 microcontroller and a 9-pin RS-232 cable which physically interfaces the evaluation board to the PC. The software provides easy access to the internal registers of the CS5531/32/33/34, and provides a means to display and evaluate the performance of the ADCs in the time domain or frequency domain.
1.2.1
Analog Section
The CS5531/32/33/34 are high precision converters designed to accurately measure up to four fully-differential analog voltage inputs while operating from a 4.9152 MHz crystal. The evaluation board provides two means of connecting external signals to the inputs of the ADCs. As shown in Figure 1, two BNC connectors (J7 and J9) along with HDR14, can be used to connect external input signals. Additionally, separate screw terminals can be used to connect signals to each of the four input channels. The input screw terminals are labeled as AINA through AIND, which correspond to different physical input channel numbers on the different parts. For the two-channel parts (CS5531 and CS5532), input A corresponds to channel 1, and input B corresponds to channel 2. For the four-channel parts (CS5533 and CS5534), input D corresponds to channel 1, input C corresponds to channel 2, input B corresponds to channel 3, and input A corresponds to channel 4. A simple RC network on each channel filters the sensor's output to reduce any interference picked up by the input leads. The 3 dB corner of the filter is approximately 50 kHz differential and common mode. The evaluation board provides three voltage reference options: VA+, the on-board LT1019, and external, as shown in Figure 2. Table 1 illustrates the options available. With HDR4's jumpers in position VA+, the reference is supplied by the VA+ and
1.2
Evaluation Board Overview
The CDB5531/32/33/34 evaluation board is partitioned into two main sections: analog and digital. The analog section consists of the CS5531/32/33/34 and a precision voltage reference. The digital section consists of the 80C51 microcontroller, 32 Kilobytes of SRAM, the hardware test switches, the reset circuitry, and the RS-232 interface. The board also has power supply connections which accommodate all of the various supply options of the CS5531/32/33/34. The evaluation board's analog section operates from either a single +5V, dual 2.5V, or dual 3V power supply. The evaluation board interfaces the
4
CDB5531/32/33/34
VA- analog supplies. With HDR4's jumpers in position LT1019, the LT1019 provides a 2.5 Volt reference (the LT1019 was chosen for its low drift, typically 5ppm/C). By setting HDR4's jumpers to position EXTERNAL, the user can supply an external voltage reference to J2's REF+ and REF- inputs. Application Note 4 on the web details various voltage references.
Reference Description Selects Analog Power Supplies HDR4
VA+ O LT1019 O REF+ O REF- O VA- O VA+ O LT1019 O REF+ O REF- O VA- O VA+ O LT1019 O REF+ O REF- O VA- O O O O O O O O O O O O O O O O VREF+ VREF+ VREF+ VREFVREFVREF+ VREF+ VREF+ VREFVREFVREF+ VREF+ VREF+ VREFVREF-
VA+
LT1019
Selects on board LT1019 Reference (5ppm/C)
These control lines are also connected to HDR2 (Header 2), which allows the user to interface an external microcontroller to the evaluation board. To accomplish this, the evaluation board must be modified in one of three ways: 1) cut the interface control traces going to the microcontroller, 2) remove resistors R4, R7, R8, and R13, or 3) remove the microcontroller. Once a method is chosen, the user can develop code for an external microcontroller using the existing analog section of the evaluation board. To aid in code development for he user's system, the source code for the on-board 80C51 microcontroller is included with the evaluation software, in the 8051Code directory that is installed as part of the setup process.
1.2.4
Power Supply Section
Selects external EXTERNAL reference source
Table 1. Voltage Reference Selection
1.2.2
Digital Section
Figures 3 and 4 illustrate the schematic of the digital section. It contains the microcontroller, test switches, a Motorola MC145407 RS-232 interface chip, and 32K bytes of SRAM. The test switches aid in debugging communication problems between the CDB5531/32/33/34 and the PC. The microcontroller, which derives its clock from a 22.1148 MHz crystal, is initially configured to communicate via RS-232 at 9600 baud, no parity, 8-bit data, and 1 stop bit. The baud rate can be changed with the software to go as fast as 115200 baud.
Figure 5 illustrates the power supply connections to the evaluation board. The VA+ post supplies the positive analog section of the evaluation board, the LT1019 and the ADC. The VA- post supplies the negative analog voltage circuitry. This terminal is connected to ground when powering the CDB5531/32/33/34 from a single +5V analog supply. The VD+ post supplies the digital section of the ADC and level shifters. The Vu+ post supplies the digital section of the evaluation board, the 80C51, the reset circuitry, and the RS-232 interface circuitry. Note, the board's digital section, supplied through the Vu+ post, must always be +5 Volts. Table 2 shows the various power connections possible with the required jumper settings on HDR3 and HDR5.
1.2.5
Headers, Jumpers, and Dip Switches
1.2.3
CS5531/32/33/34 Serial Interface
The CS5531/32/33/34 serial interfaces are SPI and MICROWIRE compatible. The interface control lines (CS, SDI, SDO, and SCLK) are connected to the 80C51 microcontroller on port one.
Table 3 describes the various headers, jumpers and DIP switches on the CDB5531/32/33/34 evaluation board. DIP switch S1 is used to control the 80C51 test modes. Table 4 illustrates the various settings of the DIP Switch S1. The DIP switches should be set to the OPEN position for normal operation. When testing the RS-232 link in the PC software,
5
CDB5531/32/33/34
Power Supplies Analog Digital +5V +5V
VA+ +5
Power Post Connections VA- AGND DGND VD+ NC GND GND +5
Jumpers Vu+ NC HDR5
Vu+ O VD+ O VD+ O VA+ O Vu+ O VD+ O VD+ O VA+ O Vu+ O VD+ O VD+ O VA+ O Vu+ O VD+ O VD+ O VA+ O Vu+ O VD+ O VD+ O VA+ O O O O O O O O O O O O O O O O O O O O O VDDD VDDD V+ V+ VDDD VDDD V+ V+ VDDD VDDD V+ V+ VDDD VDDD V+ V+ VDDD VDDD V+ V+
HDR3
VA- O A- O AGND O O DGND O DGND O DGND
+5V
+3V
+5
NC
GND
GND
+3
+5
VA- O A- O AGND O
O DGND O DGND O DGND
3V
+3V
+3
-3
NC
GND
+3
+5
VA- O A- O AGND O
O DGND O DGND O DGND
2.5V
+3V
+2.5
-2.5
NC
GND
+3
+5
VA- O A- O AGND O
O DGND O DGND O DGND
2.5V
+5V
+2.5
-2.5
NC
GND
+5
NC
VA- O A- O AGND O
O DGND O DGND O DGND
Table 2. Recommended Power Supply Connections NC = No Connection
the DIP switches should all be in the CLOSED position.
6
CDB5531/32/33/34
Name HDR2 HDR3
Function Description Used to interface with an external micro-controller Used to switch VA-, A-, and AGND to DGND.Refer to Table 2 Used to switch the voltage reference inputs from the external J2 header, to the on board LT1019 reference, or to VA+. Refer to Table 1
Default Setting Connected to 80C51 Negative Analog Power Supply Set to 0V Set to on-board LT1019 voltage reference
Default Jumpers NC
VA- O A- O AGND O VA+ O LT1019 O REF+ O REF- O VA- O Vu+ O VD+ O VD+ O VA+ O O O O O O DGND O DGND O DGND O O O O O O O O O O O O O VREF+ VREF+ VREF+ VREFVREFVDDD VDDD V+ V+
HDR4
HDR5
Used to switch Vu+, VD+, and VA+ to VDDD and/or Digital Power Supply V+. Refer to Table 2 Set to +5V Internal Use. Not Connected
HDR6, 8, 9 HDR7
Used in conjunction with the self test modes to test RS-232 Set to Normal the UART/RS-232 communication link between the Mode microcontroller and a PC. HDR10, 11, 12 Used to connect latch pins to micro-controller input. Connected Used to connect BNC AIN+ and AIN- inputs to any HDR14 Not Connected of the four input channels. DIP switch to control 80C51 test modes. See Table 4 for DIP switch settings. SW1 set to OPEN SW2 set to OPEN SW3 set to OPEN
3
NC
SW3
OPEN
S1
SW2 SW1
Table 3. Default Header and DIP Switch Descriptions
80C51 Mode Normal Operation Mode SW1 is OPEN SW2 is OPEN SW3 is OPEN RS-232 Test Mode SW1 is CLOSED SW2 is CLOSED SW3 is CLOSED
3
S1
SW3
OPEN
SW2 SW1
1
2
SW3
OPEN
3
SW2 SW1
Table 4. DIP Switch S1 Settings
1
2
1
2
7
8
R17 301 0.1%
AINA+ AIN4+
C32 J9
1 3 5 7 8 10 12 14 16 11 9 6 4 2 3 5 7 8 10 12 6 4
J17 HDR2
1
1 2
J10 HDR14
1
VA+ A2
VA+ A-
AINA+
BNC_RA
9 11
AINAAGND R18 301 0.1%
2
C2 4700PF COG .01UF COG
UCS USDI SDO USCLK A0 A1
AIN413 15
J7 BNC_RA
1
C33
AINA+ AINB+ AINC+ AIND+ AINAAINBAINCAINDJ18
AINAA2
.01UF COG
A0 ADGND
AINB+
AGND R25 301 0.1%
GUARD AIN3+
C34 C3 4700PF COG .01UF COG U3 C38 AGND R26 301 0.1% AGND
J15
AINB+
2
AINBAIN3C35 .01UF COG AGND AY2 R3 301 0.1% C29 .1UF VA+ C47 10UF .022UF COG
1
(see note)
AIN1+ AIN1AIN4+ AIN4-
AIN2+ AIN2AIN3+ AIN3VREF+ VREF-
AINBA0 A1
C22 .1UF
10UF C46 AGND
1 2 3 4 5 6 7 8 9 10 11 12
AIN1+ AIN1AIN4+ AIN4C1 C2 VA+ VAA0 A1 OSC2 OSC1 AIN2+ AIN2AIN3+ AIN3VREF+ VREFDGND VD+ /CS SDI SDO SCLK
CS5534_SSOP24
24 23 22 21 20 19 18 17 16 15 14 13
AINC+ AIN2+
C45 4.9152MHZ .01UF COG R35 AGND R12 J16 301 0.1% 301 0.1% C50 4700PF COG
CS SDI SDO SCLK
D+
J12
2
AINC+
1
C14 4700PF COG
AINCAIN2SENSE+ SENSE1 2
VREF+
C48 .01UF COG AGND
(see note)
C40 .01UF COG
AINC(see note) AIN1+
C37 AGND R28 301 0.1%
AIND+
R34
301 0.1%
VREFC49 .01UF COG AGND
J11
AIND+
.01UF COG AGND R19 301 0.1%
1
AINDAIN1C30 .01UF COG AGND
2
C15 4700PF COG
NOTE: The polari ty of the actual terminal block connections are illustrated in the block diagram on the front page of this datasheet. CS5531/32: A = C hannel 1, B = Channel 2 CS5533/34: A = C hannel 4, B = Channel 3, C = Channel 2, D = Channel 1
AIND-
CDB5531/32/33/34
Figure 1. Analog Section Schematic - Part 1
U9 DGND
19 1 20
/G1 /G2
18 17 16 15 14 13 12 11 10
VCC C44 .1UF OSC2 HDR6 A0 HDR9 DGND CS SDI SCLK
D+
2 3 4 5 6 7 8 9
UCS USDI USCLK UDCLK UA0 HDR8 R36 GND
6 5 7 3
VA+ R24 49.9 VREF+ HDR4 VA+
3 4 1 2
U4
A1 A2 A3 A4 A5 A6 A7 A8
Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8
LT1019CN8_2P5 100K
2
IN R30 10K C39 DGND 100UF TANT AR31 10K
9 10 5 6 8
OUT C16 .1UF
TC74VHC541FW
C20 .1UF
GND
TRIM HTR TEMP A7
A-
4
DGND
AAC1 .1UF U8
1 2 4 6
J2 VREF-
1
REF+
R21
2
301 0.1%
REF-
R2
301 0.1%
VCC
20 18 16 14
VDDD C41
SDO A0 HDR10 A1 HDR11 R37 R33
8 19 11 13 15 17
1/G 1A1 1A2 1A3 1A4
1Y1 1Y2 1Y3 1Y4
12
HDR12
9 7 5 3
USDO UA0 UA1
.1UF
100K 100K
2/G 2A1 2A2 2A3 2A4
2Y1 2Y2 2Y3 2Y4 GND SN74HCT244N DGND
DGND
10
DGND
CDB5531/32/33/34
Figure 2. Analog Section Schematic - Part 2
9
10
22.1184MHZ
VDDD
C24 33PF COG Y1 C7 47UF
TP14
C23 33PF COG C17 .1UF
VDDD DGND
19
C19 .1UF
DGND
UM1 AT89C5 1-20PC XTAL1
29 18
D4 1N4148
DGND
31 14 30
NRST
U2 VCC
ALE
1 2 3 9
XTAL2 EA RST R4
UCS
8-BIT MICRO 8051 PSEN ALE PROG
39
DGND
DGND
VDDD
R9
7 1
750K GND 200 1.0 P0.0
P0.0
38 2
C18
SN74HC00N R7
DGND USDI
.1UF 200
P0.1
3 4 5 6 7 8 32 33 34 36 37
R8
USDO
200 200 PORT1 PORT0
35
P0.2 P0.3 P0.4 P0.5 P0.6
DGND
R13
RESET
R16
UA0
USCLK
200 200 200 1.7 P0.7
21
R29
UA1
R32
UDCLK
S2 SW_B3W_1100 DGND P2.0 D2
1 2 7 8 24 22 23
P0.7 P2.0 P2.1 P2.2
PORT2
25 26
P2.3 P2.4 P2.5
27
3 4 5
6
P2.6
LED_555_5003
DGND
28
P2.7
10
P2.7
P3.0/RXD
11
HDR7
2 1
FROM RS-232
P3.1/TXD
12
4
3
TO RS-232
P3.2/\INT0
13
P3.2
S1
P3.3/\INT1
14
VDDD OPEN
P3.4/T0
15
3 2 1
P3.5/T1
16 SW_DIP_3
P3.6/\WR
17
P3.6
P3.7/\RD
P3.7
R10 1K
R11 1K
R1 1K
DGND
CDB5531/32/33/34
Figure 3. Digital Section Schematic - Part 1
U6 U2 VDDD P3.6 P2.5 P2.0 P2.1 P2.3 P3.7 P2.2 C43 .1UF
11 12 13
SN74HC00N
P2.6 P2.4 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 P0.0 P0.1 P0.2 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS VCC /W A13 A8 A9 A11 /G A10 /E DQ7 DQ6 DQ5 DQ4 DQ3 DGND P0.7 P0.6 P0.5 P0.4 P0.3 VDDD U1 C25 C1+ C2+ GND C2VSS RX1 TX1 RX2 TX2 RX3
11 5 6 7 8 9 4 3 2 19 20 1
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
DGND
MCM6206DP20 C27 10UF C28 10UF
DGND
U2 VCC C1VDD DO1 DI1 DO2 DI2 DO3 DI3 SN74HC00N P2.7
8 16 15 14 17 9 10
C26 10UF 10UF
18
DGND DGND
FROM RS-232 TO RS-232
13
U5 ALE P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 VCC GND DGND SN74HC373N VDDD C42 .1UF
20 10 3 4 7 8 13 14 17 18 1 11
/OC C 1D 2D 3D 4D 5D 6D 7D 8D MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q
2 5 6 9 12 15 16 19
R14 10K
12
5 9 4 8 3 7 2 6 1 10
TX3 MC145407P
J8 DE9F_RA
DGND
CDB5531/32/33/34
Figure 4. Digital Section Schematic - Part 2
11
12
DGND
CON_BANANA HDR3
1 2 4 6
VACON_BANANA
AGND
CON_BANANA
A5
3
J3
Z1 P6KE6V8P
J14 J6
47UF C5 .1UF C10
DGND AGND
AGND
AGND
AGND
AGND
DGND
Vu+
CON_BANANA
J4
Z2 P6KE6V8P C6 47UF C12 .1UF
DGND
DGND
DGND
VD+
CON_BANANA
J13
Z4 P6KE6V8P C11 47UF
C21 .1UF
DGND
HDR5
1 2 3 4
VA+ VA+
VDDD
CON_BANANA
R15 10
L2 FERRITE_BEAD
5 7
6 8
D+
J5
Z3 P6KE6V8P C8 47UF
C13 .1UF
AGND
AGND
AGND
CDB5531/32/33/34
Figure 5. Power Supply Connection Schematic
CDB5531/32/33/34
2. SOFTWARE
The evaluation board comes with software and an RS-232 cable to link the evaluation board to the PC. The evaluation software was developed with Lab Windows/CVI, a software development package from National Instruments. The software was designed to run under Windows 95 or later, and requires about 3 MB of hard drive space (2 MB for the CVI Run-Time Engine, and 1 MB for the evaluation software). After installing the software, read the readme.txt file for any last minute updates or changes. More sophisticated analysis software can be developed by purchasing the development package from National Instruments (512-794-0100).
Note: The software is written to run with 640 x 480 resolution; however, it will work with 1024 x 768 resolution. If the user interface seems to be a little small, the user might consider setting the display settings to 640 x 480 (640 x 480 was chosen to accommodate a variety of computers).
2.2
Using the Software
Before launching the software, the user should set up the CDB5531/32/33/34 evaluation board by using the correct jumper and DIP switch settings as described in the Section 1: Hardware, and connect it to an open COM port on the PC using the RS-232 serial cable. Once the board is powered on, the user can start the software package. When the software is launched, the Start-Up window appears first (Figure 6). This window contains information concerning the software's title, revision number, copyright date, etc. At the top of the screen is a menu bar which displays user options. The menu bar item Window is initially disabled to prevent conflicts with other serial communications devices, such as the mouse or a modem. After selecting a COM port, the Window menu item will become available.
2.1
1) 2) 3) 4) 5) 6)
Installation Procedure
Turn on the PC, running Windows 95 or later. Insert the Installation Diskette #1 into the PC. Select the Run option from the Start menu. At the prompt, type: A:\SETUP.EXE . The program will begin installation. If it has not already been installed on the PC, the user will be prompted to enter the directory in which to install the CVI Run-Time Engine. The Run-Time Engine manages executables created with Lab Windows/CVI. If the default directory is acceptable, select OK and the Run-Time Engine will be installed there. After the Run-Time Engine is installed, the user is prompted to enter the directory in which to install the CDB5531/32/33/34 software. Select OK to accept the default directory, or choose an alternate directory. Once the program is installed, it can be run by double clicking on the Eval5531/32/33/34 icon, or through the Start menu.
2.3
Selecting and Testing a COM Port
7)
8)
Upon start-up, the user must select the serial communications port which will interface to the CDB5531/32/33/34 board. To select a COM port, pull down the Options menu, and select Data Source. The Data Source Window will appear on the screen, with a variety of options. Check the box labeled "Communications Port" and then select either COM1 or COM2 in the box which is initially labeled "NONE" (the "File" box is used for previously saved files, and is discussed later). Testing the COM port to verify communication between the PC and the evaluation board is not necessary, but can help to troubleshoot some problems. The procedure for testing the communication link follows.
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CDB5531/32/33/34
1) Press the TEST RS-232 button in the Data Source Window. 2) When prompted, set the three DIP switches to the closed position, reset the board by pressing the reset switch, and press OK to perform the test. 3) If the test passes, set the DIP switches back to the open position, and reset the board by pressing the reset switch again. This returns the evaluation board to normal operating mode. 4) If the test fails, check the serial port connections, power connections, jumpers, and DIP switch settings on the board, and run the test again from step 1. Note: When performing the RS-232 test, the communications speed is reset to the default 9600 baud rate. The user can change the speed of the serial link at any time by clicking on the box that reads "9600", and selecting a new speed. Once the serial link has been established between the PC and the evaluation board, the user can press the "Done" button to return to the Start-Up Window. tion Register's meaning is also decoded in this window. Update Registers Button: The Update Registers button will read all the register values from the part and update the hexadecimal values displayed on the screen. This usually takes a couple of seconds, but it is a good idea to press the Refresh Screen button when entering the Setup Window, or after modifying any registers to reflect the current status of the part. Configuration Register: In the Configuration Register box, the contents of the Configuration Register are displayed, and can be modified by typing a hexadecimal value in the HEX: box, or by changing any of the values below the HEX: box to the desired settings. Note: When changing the value of the reset system bit to `1' (RS, bit 29 in the Configuration Register), the part will be reset, and all registers will return to their default values. It is a good idea to press the Update Registers button after performing a reset to update the screen with the new register values. Channel Setup Registers: In the Channel Setup Registers box, all four Channel Setup Registers are displayed in hexadecimal. These registers can be modified from the Channel Setup Register Window, which is accessed by pressing the Edit CSRs button. Channel Setup Register Window: In the Channel Setup Register Window (Figure 8), each of the four CSRs can be decoded and modified. The blue box at the top of the window allows the user to switch between CSRs. Each 32-bit CSR contains two 16bit "Setups" which are decoded in the two boxes below the hexadecimal value. The currently displayed CSR can be modified by either typing a value directly in the Hexadecimal: box or by changing the decoded values in the individual Setup boxes. Offset / Gain Registers: In the Offset Registers / Gain Registers box, the offset and gain registers for all channels are displayed in hexadecimal (two
2.4
Selecting a Part
To ensure proper functionality of the evaluation board and software, the user must select the part that they are using. To select a part, pull down the Options menu and select Part. From this menu, click on the part that is installed on the CDB5531/32/33/34.
2.5
Register Access in the Setup Window
The Evaluation software provides access to the CS5531/32/33/34's internal registers in the Setup Window (Figure 7). The user can enter the Setup Window by pulling down Window and selecting Setup Window, or by pressing F2 on the keyboard. In the Setup Window, all of the ADC's registers are displayed as hexadecimal values. The Configura-
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CDB5531/32/33/34
channels for the CS5531 and CS5532, four channels for the CS5533 and CS5534). These registers can all be modified in the Calibration Window, which is accessed when the user presses the Calibration Window button. Calibration Window: The Calibration Window (Figure 9) permits the user to access the calibration registers for each channel of the CS5531/32/33/34 and also perform self and system offset or gain calibrations on of the channels. Prior to performing calibrations however, the Channel Setup Registers should be modified to configure the part for the desired operating mode (see the section on the Channel Setup Register Window for more details). Note that offset calibration should be performed before gain calibration to ensure accurate results. Refer to the CS5531/32/33/34 Data Sheet for more details. Self Offset or Gain Calibrations: 1) Pull down the Self Offset or Self Gain box, and select the setup number you want to use to calibrate the channel. 2) The offset and gain register values will automatically update when the calibration is completed. System Offset Calibrations: 1) Attach a grounded input to the physical channel you want to calibrate. Note that the grounded input must be within the common mode range of the particular amplifier (1X64X) for valid calibration. 2) Pull down the System Offset box, and select the setup number you want to use to calibrate the channel. 3) The offset and gain register values will automatically update when the calibration is completed. System Gain Calibrations: 1) Attach a full-scale input to the physical channel you want to calibrate. 2) Pull down the System Gain box, and select the setup number you want to use to calibrate the channel. 3) The offset and gain register values will automatically update when the calibration is completed. Reset Serial Port: When this button is pressed, the software will send the synchronization sequence discussed in the CS5531/32/33/34 data sheet to the ADC. This sequence brings the CS5531/32/33/34's serial port back to the command mode. It does not reset any of the registers in the part. Reset Part Button: When this button is pressed, a `1' is written to the RS bit in the Configuration Register to reset the part. After a reset, the registers will all return to their default values as discussed in the CS5531/32/33/34 data sheet. Read Data Button: This button will instruct the ADC to begin performing repeated single (fullysettled) conversions on the setup channel specified by the Setup Register box. The results of the most recent conversion are displayed in the "Last Conversion" box, as well as the Channel and Overflow indicator bits for each conversion. The software will halt the data collection process when the user presses the Stop button. Num to Avg. Box: This box will allow the user to collect multiple single conversions at once, and the software will compute mean, standard deviation, and peak values for each set of conversions. The results will be displayed in the corresponding boxes for the last three sets of data taken.
2.6
Data Collection Window Overview
The Data Collection Window (Figures 10, 11, and 12) allows the user to collect sample sets of data from the CS5531/32/33/34 and analyze them using time domain, FFT, and histogram plots. The Data Collection Window is accessible through the Window option, or by pressing F3.
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CDB5531/32/33/34
Time Domain / FFT / Histogram Selector: This menu selects the type of data processing to perform on the collected data and display in the plot area. Refer to the section on Analyzing Data for more information. Collect Button: This button will collect data from the part, to be analyzed in the plot area. See the section on Collecting Data Sets for more information. Config Button: This button will bring up the configuration window, in which the user can modify the data collection specifications. See the discussion of the Config Window in this document. Output Button: This button will bring up a window in which the user can output the data to a data file for later use, print out a plot, or print out the entire screen. Zoom Button: This button allows the user to zoom in on the plot by selecting two points in the plot area. Press the Restore button to return to the normal data plot, or press the Zoom button again to zoom in even further. Setup Select Box: This box determines the setup number to use when performing conversions. See the CS5531/32/33/34 data sheet for more details on the functionality of the Channel Setup Registers. FFT Window: This box allows the user to select the type of windowing algorithm for FFT processing. Windowing algorithms include the Blackman, Blackman-Harris, Hanning, 5-term Hodie, and 7term Hodie. The 5-term Hodie and 7-term Hodie are windowing algorithms developed at Cirrus Logic. This selection has no effect on Time Domain or Histogram analysis. Histogram Bin Width: This box allows for a variable "bin width" when plotting histograms of the collected data. Each vertical bar in the histogram plot will contain the number of output codes contained in this box. Increasing this number may allow the user to view histograms with larger input ranges. Collection Process: This box will change the collection process to either buffered or un-buffered. For buffered conversions, the microcontroller will temporarily store the conversion data in the onboard 32 KB SRAM. For unbuffered conversions, the microcontroller will send the collected data directly to the PC through the RS-232 cable. Note that unbuffered conversion sets are limited by the speed of the RS-232 connection, while buffered sets are limited to 8192 samples by the size of the on-board SRAM. Crystal Frequency: The evaluation board comes equipped with a 4.9152 MHz crystal. If the user chooses to replace this with a crystal of a different frequency, the number in this box can be modified to provide more accurate timing and FFT information. Accept Button: When this button is pressed, the current settings will be saved, and the user will return to the Data Collection Window.
2.7
Config Window
The Config Window allows the user to set up the data collection and analysis parameters. Number of Samples: This box allows the user to select the number of samples to collect, between 16 and 32,768. Due to the 32 KB memory size on the CDB5531/32/33/34, the maximum is 8192 samples when collecting memory-buffered sample sets. When collecting un-buffered sample sets, the only limitation is the speed of the RS-232 interface. Average: When doing FFT processing, this box will determine the number of FFTs to average. FFTs will be collected and averaged when the Collect button is pressed.
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2.8
Collecting Data Sets
To collect a sample data set: 1) In the Data Collection Window, press the Config button to bring up the Configuration Window and view the current settings.
CDB5531/32/33/34
2) Select the appropriate settings from the available options (see the section on the Configuration Window) and press the Accept button. 3) The Data Collection Window should still be visible. In the Setup box, select the Setup number you want to use to perform conversions. 4) Press the Collect button to begin collecting data. A progress indicator bar will appear at the bottom of the screen during the data collection process. 5a) For buffered conversion sets, data is first collected from the CS5531/32/33/34 and stored in SRAM, and then transferred from the SRAM to the PC through the RS-232 serial cable. Depending on the value of the WR bits in the selected Setup and the number of samples being collected, this process may take a long time. The process can be terminated by pressing the Stop button, but if this is done the user should also press the Reset button on the CDB5531/32/33/34 board to bring the microcontroller out of the collection routine. 5b) For unbuffered conversion sets, data is sent directly to the PC through the RS-232 serial cable. Depending on the value of the WR bits in the selected Setup and the number of samples being collected, this process may take a long time. The process can be terminated by pressing the Stop button, but if this is done, the user should also press Reset on the CDB5531/32/33/34 board to bring the microcontroller out of the collection routines. 6) Once the data has been collected, it can be analyzed, printed, or saved to disk. 1) Output Data File: Brings up the File Save dialog box, which allows the data to be saved to a file. 2) Print Screen: Prints the entire display, including the calculated statistics. 3) Print Graph: Prints the information in the plot area. The statistical information is not printed.
2.10
Retrieving Saved Data From a File
To load a previously saved file: 1) Pull down the Setup option and select Disk. A file menu will appear. 2) Find the data file in the list and select it. Press the Select button to return. 3) Go to the Data Collection Window, and press the Collect button. 4) The data from the file should appear on the screen. To select a different file, repeat the procedure.
2.11
Plot Options Window
The plot options window can be accessed by pulling down the Options menu and clicking on Plot Options. In this window, the user can change the background color, the plot line color, and the peak indicator color. The harmonic and peak indicators can also be turned on or off in this window.
2.12
Analyzing Data
2.9
Saving and Printing Data
Once collected, data can be printed or saved to a file for later use. To save or print data, click on the Output button in the Data Collection Window. A small panel will pop up with three options:
The evaluation software provides three types of analysis tests - Time Domain, Frequency Domain, and Histogram. The Time Domain analysis processes acquired conversions to produce a plot of Conversion Sample Number versus Magnitude. The Frequency Domain analysis processes acquired conversions to produce a magnitude versus frequency plot using the Fast-Fourier transform (results up to Fs/2 are calculated and plotted). Also, statistical noise calculations are calculated and displayed. The Histogram analysis test processes acquired conversions to produce a histogram plot.
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CDB5531/32/33/34
Statistical noise calculations are also calculated and displayed. For more information on Histogram or FFT analysis, refer to Application Notes 37 and 147. FREQUENCY: Displays the x-axis value of the cursor on the FFT display. MAGNITUDE: Displays the y-axis value of the cursor on the FFT display. S/D: Indicator for the Signal-to-Distortion Ratio, 4 harmonics are used in the calculations (decibels). S/N+D: Indicator for the Signal-to-Noise + Distortion Ratio (decibels). SNR: Indicator for the Signal-to-Noise Ratio, first 4 harmonics are not included (decibels). S/PN: Indicator for the Signal-to-Peak Noise Ratio (decibels). # of AVG: Displays the number of FFT's averaged in the current display.
2.13
Histogram Information
The following is a description of the indicators associated with Histogram Analysis. Histograms can be plotted in the Data Collection Window by setting the Time Domain / FFT / Histogram selector to Histogram (Figure 12). BIN: Displays the x-axis value of the cursor on the Histogram. MAGNITUDE: Displays the y-axis value of the cursor on the Histogram. MAXIMUM: Indicator for the maximum value of the collected data set. MEAN: Indicator for the average of the data sample set. MINIMUM: Indicator for the minimum value of the collected data set. STD. DEV.: Indicator for the Standard Deviation of the collected data set. VARIANCE: Indicates the Variance for the current data set.
2.15
Time Domain Information
The following controls and indicators are associated with Time Domain Analysis. Time domain data can be plotted in the Data Collection Window by setting the Time Domain / FFT / Histogram selector to Time Domain (Figure 10). COUNT: Displays current x-position of the cursor on the time domain display. MAGNITUDE: Displays current y-position of the cursor on the time domain display. MAXIMUM: Indicator for the maximum value of the collected data set. MINIMUM: Indicator for the minimum value of the collected data set.
2.14
Frequency Domain Information
The following describe the indicators associated with FFT (Fast Fourier Transform) Analysis. FFT data can be plotted in the Data Collection Window by setting the Time Domain / FFT / Histogram selector to FFT (Figure 11).
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CDB5531/32/33/34
Figure 6. Start-Up Window
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CDB5531/32/33/34
Figure 7. Setup Window
Figure 8. Channel Setup Register Window
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CDB5531/32/33/34
Figure 9. Calibration Window
Figure 10. Data Collection Window: Time Domain Analysis
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CDB5531/32/33/34
Figure 11. Data Collection Window: FFT Analysis
Figure 12. Data Collection Window: Histogram Analysis
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CDB5531/32/33/34
3. PCB LAYOUT
The CS5531/32/33/34 should be placed entirely over an analog ground plane. Place the analog-digital plane split immediately adjacent to the digital portion of the chip. Figures 14 and 15 illustrate the layout of the CDB5531/32/33/34. Note: See Applications Note 18 for more detailed layout guidelines. Before layout, please call for our Free Schematic Review Service.
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CDB5531/32/33/34
Figure 13. Top Silkscreen
CDB5531/32/33/34
Figure 14. Top Side Layout
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CDB5531/32/33/34
Figure 15. Bottom Side Layout
* Notes *

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